Modern interrupt controllers are powerful chips that can more than merely arbiting many interrupt sources onto a single processor. Due a software interface, the route of an interrupt can be prescribed and constrained to a large degree.: They allow to prioritize interrupt sources and to distribute the IRQs onto multiple processors, which can also be assigned a priority.
However, all designs employed in actual common-of-the-shelve hardware lacks one important property: They are not priority-obedient. This means that the highest-priority interrupt is not guranteed to be routed to the processor with the lowest priority in the whole system. Especially for real-time systems, this shortcomming poses a difficult starting point to implement a absolutely priority obedient system. If the ground is shaking, its hard to build a stable house.
In previous work, we have already designed a priority-obedient priority controller. The task of this thesis is to integrate the given design into the Rocket softcore, which implements the RISC-V instruction set architecture. Part of the thesis is also to build an appropriate test bed to use the IRQ controller.