Supporting the RISC-V Architecture in the SysWCET Static Analysis Infrastructure
- Typ der Arbeit: Masterarbeit
- Status der Arbeit: offen
- Projekte: AHA
- Betreuer: Christian Dietrich, Peter Wägemann, Peter Ulbrich
Determining the worst-case response time in real-time systems is a crucial but very challenging problem. This problem of determining upper bounds of the execution time becomes especially complicated when considering synchronous events~(e.g., task switches) asynchronous system~(e.g., ISRs). In the SysWCET approach with the underlying global control-flow graph, we demonstrated the possibility to determine such worst-case response time estimates for an architecture with very limited complexity (i.e. the PATMOS platform).
This thesis adds support for the RISC-V processor architecture to the existing SysWCET infrastructure. The main problem addressed in this thesis is precisely modeling of the caching behavior. For example, a context switch, which leads to the execution of a different thread, potentially evicts the data and instruction cache of the CPU. The analysis techniques inside SysWCET need to respect such state transitions inside the global control-flow graph to finally determine safe upper bounds.
- Fundamentals in real-time systems
- Knowledge about computer architectures
- Interest in compilers (CLang/LLVM)
- C, Ruby
Relevant Previous Work
OSEK-V: Application-Specific RTOS Instantiation in Hardware
Proceedings of the 2017 ACM SIGPLAN/SIGBED Conference on Languages, Compilers and Tools for Embedded Systems (LCTES '17)ACM Press2017.
Global Optimization of Fixed-Priority Real-Time Systems by RTOS-Aware Control-Flow Analysis
ACM Transactions on Embedded Computing Systems16.2ACM Press2017.